Analog pre-processor

ABSTRACT

An analog circuit  20  includes an amplifier  30  with a positive input node, a negative input node, a positive output node and a negative output node. A first capacitor  32  is coupled between the negative input node and an analog signal node. A second capacitor  34  is coupled between the positive input node and a reference voltage node. In addition, a third capacitor  36  is coupled between the positive input node and the negative output node and a fourth capacitor  38  is coupled between the negative input node and the positive output node. A first switch  40  is coupled between the third capacitor  36  and the negative output node and a second switch  42  is coupled between the fourth capacitor  38  and the positive output node.

FIELD OF THE INVENTION

[0001] This invention relates generally to electronic circuits andspecifically to an analog pre-processor that can be used with a digitalimaging device.

BACKGROUND OF THE INVENTION

[0002] Digital cameras are fast replacing film based cameras as a mediumto capture and store images. In a digital camera, a light sensorconverts the incident light into voltage. The analog front end (AFE)first processes the signal to improve dynamic range and subsequentlydigitizes this voltage. The digital output is then processed further andstored so it can be viewed in various forms.

[0003] The main thrust in digital camera research is to improve picturequality and reduce power. The analog front end is one of the key blockswhich determines the overall accuracy and power of the camera system.The AFE can be conceptually divided into two parts, the analog signalprocessing section (referred to here as the analog pre-processor or APP)followed by a digitizer (e.g., an analog-to-digital converter or ADC).

[0004] For hand-held digital cameras and camcorders, a significantperformance criteria is power, for a given accuracy. Camera vendors arelooking for very low power twelve-bit analog front ends. For example,one goal is to produce sub-80 mW AFEs. This goal represents a powerreduction of about one third compared to commercially available devices.

SUMMARY OF THE INVENTION

[0005] In one aspect, the present invention provides an analogpre-processor that achieves both low power and high accuracy. Forexample, the preferred embodiment provides a single operationalamplifier (op amp) based architecture that minimizes analog power aswell as provides optimum noise and linearity. This device is followed bya very low power twelve-bit analog to digital converter to complete thefront end.

[0006] The present invention is useful in a number of applicationsincluding in a digital imaging device such as a digital camera orcamcorder. This application might include a light sensor such as acharge coupled device (CCD) or a CMOS integrated sensor (CIS).Electrical signals corresponding to received light is provided to ananalog pre-processor. In the preferred embodiment, the analogpre-processor includes a single amplifier. After the pre-processing, thesignal can be converted to a digital signal and further processed priorto being displayed and/or stored.

[0007] In a more specific embodiment, the analog pre-processor is ananalog circuit that includes an amplifier with a positive input node, anegative input node, a positive output node and a negative output node.A first variable capacitor is coupled between the positive input nodeand an analog signal node. A second variable capacitor is coupledbetween the negative input node and a reference voltage node. Inaddition, a third variable capacitor is coupled between the positiveinput node and the negative output node and a fourth variable capacitoris coupled between the negative input node and the positive output node.A first switch is coupled between the third variable capacitor and thenegative output node and a second switch is coupled between the fourthvariable capacitor and the positive output node.

[0008] The preferred embodiment includes a number of advantages overalternative solutions. For example, the pre-processor utilizes verylittle power. This low power is accomplished while maintaining good PGA(programmable gain amplifier) linearity. In addition, the noise iscomparable or better than other twelve-bit parts.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above features of the present invention will be more clearlyunderstood from consideration of the following descriptions inconnection with accompanying drawings in which:

[0010]FIG. 1 is a block diagram of an exemplary digital imaging device;

[0011]FIG. 2 is a block diagram illustrating the gain distribution of apreferred analog front end;

[0012]FIG. 3 shows the timing of an exemplary CCD input;

[0013]FIG. 4 shows a first embodiment analog pre-processor;

[0014]FIG. 5 shows a second embodiment pre-processor;

[0015]FIG. 6 shows a two-stage amplifier;

[0016]FIG. 7 shows the amplifier characteristics of the two stages;

[0017]FIGS. 8a-8 c show a more detailed implementation of a preferredembodiment two-stage amplifier; and

[0018]FIGS. 9 and 10 illustrate the gain performance of the analogpre-processor.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0019] The making and use of the various embodiments are discussed belowin detail. However, it should be appreciated that the present inventionprovides many applicable inventive concepts which can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative of specific ways to make and use the invention,and do not limit the scope of the invention.

[0020] The present invention will be described in the context of adigital imaging device, such as a digital camera. Accordingly, a systemwill first be described followed by a very specific implementation ofthe system. It should be understood that the present invention is notlimited to the specific implementation described here.

[0021]FIG. 1 illustrates a block diagram of a digital imaging device 10such as a digital camera (moving or still). A light sensor 12 receivesincoming light. In the preferred embodiment, the light sensor includes amatrix array (e.g., provided in rows and columns) of light sensingunits. The light sensor can convert two-dimensional incident light intovoltage signals. In the preferred embodiment, these voltage signals areoutput in a serial fashion so that each pixel received by the sensor isoutput. The preferred embodiment utilizes a charge coupled device (CCD).One such commercially available CCD is the ICX2882AQ manufactured bySony. Other embodiments may use other light sensors, such as a CMOSintegrated sensor, as an example.

[0022] The analog output of the light sensor is provided to an analogfront end (AFE) 14. The analog front end, which will be discussed ingreater detail below, processes the analog signal and provides a digitaloutput. The digital output can be provided to a digital processingcircuit 16 such as a digital signal processor (DSP) or an applicationspecific integrated circuit (ASIC), which can optionally perform furthersignal processing. As an example, a preferred embodiment implementationcan include a DSP manufactured by Texas Instruments Incorporated.Representations of the light image can then be provided to a storagedevice (e.g., video tape, EEPROM, magnetic disk, optical disk), adisplay (e.g., liquid crystal display or LCD, cathode ray tube or CRT),or other destination such as a communication port for transmission. Asexamples, the output of the camera can be sent to a computer, a storagemedia, a printer, a display, a network, or a recorder.

[0023] The AFE 14 can be conceptually divided into two parts, the analogsignal processing section (referred to here as the analog pre-processoror APP) followed by a digitizer (e.g., an analog-to-digital converter orADC). In the preferred embodiment, the APP should be able to perform thefollowing functions, among other things:

[0024] Correlated Double Sampling (CDS)

[0025] Programmable Gain Amplification (PGA)

[0026] Single ended to differential conversion

[0027] Level Shifting

[0028] Offset cancellation

[0029] It is understood, however, that an apparatus or method thatprovides fewer than all of these features (or even none of the features)can still include the inventive concepts as disclosed herein.

[0030] In many applications, the main performance criteria for the AFEare low noise and low power, which, in the case of a digital camera,lead to improved picture quality and longer battery life. It has beenperceived that there is a big market for a twelve-bit, 21 MSPS (megasamples per second), sub 80 mW AFE for digital still cameras. In thisrespect, the present invention has been utilized in a digital stillcamera front-end chip (TAFE1221) that can achieve a power of 65 mW. Thenoise performance is also comparable or better than other twelve bitparts. The following paragraphs discuss the design challenges andproblems solved to achieve the above.

[0031] Low power can be achieved by designing a low power ADC and a lowpower APP section. In the preferred implementation, one goal of the APPis to provide 36 dB of gain at a step size of 0.05 dB along withcorrelated double sampling and single ended to differential conversion.These goals have been conventionally implemented using several cascadedstages built around operation amplifiers (OPAMPs), which leads to highpower and noise. In the preferred implementation design, on the otherhand, the entire APP functionality has been implemented using a singleOPAMP stage. This approach uses minimum power and also minimizes channelnoise.

[0032]FIG. 2 illustrates a block diagram of an AFE 12 than can achievethis goal. In this design, the APP 20 has been designed to provide 0 to24dB of gain at 1 dB step. After the signal has been digitized by ADC22, a digital multiplier 24 provides the finer step of 0.05 dB with arange of 1 dB. Another crude digital gain block 26 provides theremaining 12 dB gain at a step of 6 dB. It can be shown that thisconfiguration provides adequate noise performance for a twelve-bitsystem.

[0033]FIG. 3 shows the signal input from the light sensor 12 to theanalog front end 14. In this example, the light sensor is a CCD. Thefirst line, labeled CCD output, shows a typical CCD output waveform. TheCCD output is reset to a fixed voltage (most positive in the waveform).Then the reset switch (shown and described in more detail with respectto FIG. 4) is opened (at the falling edge of signal SR) and subsequentlythe signal becomes available (at the falling edge of signal SV). Thesignals SR and SV are usually generated by a timing chip which controlsboth the CCD and AFE. The CCD voltage levels are of the order of 10volts or more. Due to this, capacitive coupling (e.g., clamping) betweenthe CCD chip and the AFE chip is preferably utilized.

[0034] In order to achieve correlated double sampling, the CCD output issampled twice. The first sample is taken when the reset switch is turnedoff (e.g., at the falling edge of signal SR) and the second sample istaken after the pixel charge is dumped on to the CCD summing capacitor(e.g., at the falling edge of signal SV). These two sample points arelabeled with the numbers (1) and (2) in FIG. 3. The difference betweenthese two voltages provides the true signal. This method of taking twosamples and taking their difference to remove the reset noise isreferred to as correlated double sampling (CDS). CDS is useful since iteliminates the kT/C noise sampled on the CCD output capacitor as well aslow frequency noise.

[0035] In order to utilize the full range of the analog-to-digitalconverter 22, the CCD signal range is preferably matched to the inputrange of the ADC. This goal requires that the CCD signal be gained (orattenuated) by the required amount. The signal range of the CCD istypically on the order of 1.5 V while, for the design example describedhere, the ADC range is on the order of 2.6V. Thus, a minimum gain of2.6/1.5=1.73 (4.78 dB) is desired in this design. In addition to thisgain, the system should have between about 0 and 24 dB gain. Thus theAPP 12 is specified to provide a gain of 4.78 dB to 28.78 dB at 1 dBstep. Also, since the overall accuracy goal is to be accurate to about0.05 dB, the gain steps should also be accurate to within +/−0.05 dB.

[0036] As shown in FIG. 3, the CCD output is single ended, going to mostpositive during reset and then coming down an amount that depends on thestrength of the optical signal received. In the preferred embodiment,this input is converted to fully differential by the APP circuitry. Thisconversion applies a gain of 2× to optimize dynamic range. Prior toapplying the gain, a DC level shifting of half the ADC input range isdone. This shift is applied since the input is single ended and singlesided without having a fixed common mode voltage.

[0037] The APP 12 has additional circuitry to take an analog voltage(usually provided by a DAC) and subtract it from the output. In thismanner, the circuitry can cancel offset. During offset cancellation, thelevel shifting is suppressed to provide range for negative offsets.

[0038] The foregoing system specifications pose several challenges forthe design. The issues come mainly from three requirements, namely,large gain range, high speed, and the nature of the CCD waveform. Eachwill now be discussed.

[0039] The goal of programmable gain amplification (PGA) requires a gainrange of 4.78 dB to 28.78 dB at step of 1 dB with an accuracy of 0.05 dBaround each gain point. The gain also should be linear in dB scale.These goals have been addressed by careful choice of capacitor ratiosfor each gain step, to achieve required accuracy with minimum loading.This goal also creates problem for amplifier design, as the amplifierclose loop feedback factor changes over a wide range, creating stabilityproblems. This problem has been addressed by changing the amplifier openloop gain and bandwidth with PGA gain using digital control.

[0040] The goal of having high speed has been addressed by choosing acascaded 2 stage amplifier topology. This amplifier is described ingreater detail below (see e.g., FIGS. 6-8 and related text).

[0041] As discussed above, the CCD waveform is preferably sampled usingcorrelated double sampling. Since the preferred embodiment implementsthis technique using a single amplifier stage, the architecture requiresthe amplifier to operate over a large input common mode range. To reducethe effect, an inverter has been used as a common mode amplifier tocounter the input common mode swing. A pre-amplifier section that iscapable of handling wide swing is preferably used. Also, capacitivecoupling is used within stages to interface the pre-amplifier with thefollowing main amplifier.

[0042] A first embodiment of the analog pre-processor 20 will now bedescribed with respect to FIG. 4. An amplifier 30 preferably comprisesan operational amplifier, for example a single operational amplifierincluding two amplifier stages. A first sampling capacitor 32 is coupledbetween a negative input node of the amplifier 30 and an analog signalnode, labeled in FIG. 4 as CCD IN since it is coupled to the output ofthe CCD 12 in the preferred embodiment. A second sampling capacitor 34is coupled between the positive input node of amplifier 30 and areference voltage node (e.g., ground). In the preferred embodiment, thesampling capacitors 32 and 34 are variable capacitors. In an alternateembodiment, the analog input (e.g., CCD IN) could be coupled to thepositive input node while the reference node is coupled to the negativeinput node.

[0043] Feedback capacitors 36 and 38 are coupled between the input andoutput nodes of amplifier 30. For example, feedback capacitor 36 iscoupled between the negative input node and positive output node andfeedback capacitor 38 is coupled between the positive input node and thenegative output node. Hold switches 40 and 42 are coupled in therespective paths of feedback capacitors 36 and 38. While illustratedbetween the feedback capacitor 36 (38) and the positive (negative)output node, it is understood that the switch 40 (42) couldalternatively be disposed between the feedback capacitor 36 (38) and thenegative (positive) input node. Switches 40 and 42 are preferablyn-channel MOS transistors.

[0044] The APP can be reset by use of switches 44, 46, 48 and 50. Theseswitches are also preferably n-channel MOS transistors. Accordingly,switches 44 and 48 are arranged to selectively couple the two plates offeedback capacitor 36 to an input common mode node V_(INCM). Similarly,switches 46 and 50 are arranged to selectively couple the two plates offeedback capacitor 38 to the input common mode node V_(INCM).

[0045] The manner in which the CDS functions can be implemented will nowbe described with respect to FIG. 4. During reset, the signals S and SPcause their corresponding switches (48 and 50 for signal S and 44 and 46for signal SP) to be ON (i.e., conductive). During this period, the CCDoutput is sampled on the sampling capacitors 32 and 34. These switches44, 46, 48 and 50 are then turned OFF (i.e., rendered non-conductive) atthe falling edge of signal SP (for switches 44 and 46) and signal S (forswitches 48 and 50). The falling edge of signal SP occurs just beforethe falling edge of signal S. At this time, the sampling capacitors 32and 34 continue to be connected to the CCD output (CCD IN) and theamplifier 30 enters the HOLD mode since switches 40 and 42 are turnedON. The amplifier output OUTP, OUTM now follows the change in the CCDoutput. The output voltage, at the end of the HOLD period, will be thedifference of that CCD output voltage sampled at that falling edge ofsignal SR and again at the falling edge of signal SV (see FIG. 3).

[0046] Since the CCD output is single ended, the sampling capacitor 34is always grounded. The negative input of the amplifier 30 is broughtout at the pin and connected through capacitor 34 to the CCD ground pin(not shown). This way, the amplifier input is made pseudo differentialand most of the noise picked up gets cancelled out. The amplifier 30output is set to a fixed common mode by a separate output common modeloop. Thus, the output is differential around a fixed common mode,though the input is single ended. To take care of the increased dynamicrange, an inherent gain of 2× is provided by the stage. A more specificimplementation of a preferred embodiment APP circuit is shown in FIG. 5.

[0047] To obtain programmable gain, a number of capacitors are connectedin parallel to serves as sampling capacitors (Csapp) 32 and 34 andfeedback capacitors (Cfapp) 36 and 38. Using a number of capacitorsallowed the effective capacitor to be variable. To simplify thedrawings, only one such capacitor is shown in each instance but it isunderstood that any number of capacitors and corresponding switches canbe included. Resolution can be increased by including a larger number ofcapacitors for each variable capacitor 32, 34, 36 and/or 38.

[0048] The gain is given by Csapp/Cfapp. To select these capacitors 32and 34, switches 82 and 84, respectively, are provided at the platenearest the amplifier 30 input node. While this location is notrequired, it is preferred since this node sees a constant voltage, andhence has a constant switch resistance irrespective of the inputvoltage. On the other hand, if the switches 82 and 84 are placed on theinput side, the resistance would be signal dependent and would causesome degree of distortion. If the capacitor 32 or 34 is not selected, itis connected to a fixed voltage source V_(INCM) by switch 86 or 88. Asnoted above, the dotted lines extending from each capacitor 32, 34 isintended to signify that any number of capacitors can be used. For eachof the capacitors, the respective switch 82-88 will independentlycontrollable. Thus the CCD sees a fixed load irrespective of the gain.The amplifier also sees a fixed load.

[0049] Unique ratios of capacitors are used to generate gain linear indB scale. The capacitors 32, 34, 36 and 38 are preferably implemented asa square matrix of unit cells to improve matching accuracy. Thecapacitor values can be chosen through a software program. The algorithmhas the following features

[0050] For each k between 0 and 24, generate Cs(k)/Cf(k) within givenaccuracy

[0051] Minimize max(Cs(k)) and max(Cf(k))

[0052] Keep the change of capacitance between adjacent step(Cs(k+1)−Cs(k)) as low as possible to improve matching.

[0053] A disadvantage of the APP configuration described thus far isthat the amplifier 30 input common mode changes with the signal swing.Due to this variation, the amplifier should have a large input commonmode range. The situation is worse for large input signal swing (lowgain). To reduce this effect, an inverter 52 can be used for low gainsettings as an inverting common mode amplifier. The inverter 52 drivescommon mode capacitors (Cint) 54 and 56. Thus, when the input swing islarge, the resultant common mode movement is countered by the inverter52 output. Since this output need not be linear, an inverter 52 sufficesas an amplifier. Since the amplifier 30 is designed to work at highergain setting, the reduced bandwidth is still sufficient for settling.

[0054] To obtain the offset cancellation, additional capacitors (Coff)58 and 60 are provided. In digital camera systems, for example, the DSP(or additional digital circuitry in the AFE chip) measures the offset ofthe channel by observing the ADC output. This digital value is thenconverted into an analog voltage using a DAC (not shown) and subtractedin the analog domain. Here, the DAC output CDAC is fed to the Coffcapacitors, thus subtracting the offset at the APP output.

[0055] During the SR phase, these capacitors 58 and 60 are shorted (zeroinput differential). During the hold phase, the Coff capacitors 58 and60 sample the offset DAC (not shown). The reason for this is that thehold phase is much longer, hence the coarse DAC has much more time tosettle. Since the voltage subtracted should be independent of gain, anumber of capacitors are provided such that Ccoff/Csapp is constant.

[0056] The ADC 22 converts analog signals to digital signals. The analogvoltage range is defined by the two voltage references Vrefp and Vrefm(this is generated on-chip). Thus for input Vin=(Vrefp−Vrefin), ADCoutput is maximum (all 1's, in digital terms) and for inputVin=−(Vrefp−Vrefm), ADC output is minimum (all 0's). Note that the ADCis fully differential, hence Vin=(INP−INM), which goes both positive andnegative.

[0057] In the embodiment of FIG. 5, the feedback capacitors 36 and 38(Cfapp) are not connected to a common voltage V_(incm) during sampling.Instead they are connected to voltage node V_(REFP), V_(REFM). Thisprovides the required level shift. During offset cancellation loop, thelevel shift is turned OFF by connecting the feedback capacitors tocommon mode.

[0058] The overall transfer function for the APP is given by$V_{CDS} = {{\left( {V_{VIDEO} - V_{RESEl}} \right) \cdot \frac{Csapp}{Cfapp}} - {\frac{C_{OFF}}{Cfapp} \cdot V_{CDAC}} - {\Delta \quad V_{REF}}}$where  Δ  V_(REF) = V_(REFP) − V_(REFM).

[0059] The load seen by the amplifier is a parallel combination of (1)the feedback capacitance Cfapp in series with parallel combination ofthe sampling capacitance Csapp, the DAC capacitance Cdac, and parasiticcapacitance Cpar; (2) ADC sampling capacitor in parallel with inputcapacitance of comparators; and (3) amplifier's output parasiticcapacitance. This is a varying load with gain. For lower gains, feedbackcapacitance Cfapp is comparable to sampling capacitance Csapp, resultingin higher capacitive load. Effective capacitive load falls with gain asCf gets smaller.

[0060] For the preferred embodiment design, assuming 12 bit settling,the closed loop bandwidth requirement is about 53 MHz. The maximumanalog gain is 28.78 dB. This corresponds to a closed loop feedbackfactor of 35.2 (along with parasitics of the present design), whichcorresponds to 31 dB.

[0061] The DC gain for a twelve-bit corresponds to about 72 dB. Sincethe feedback factor is 31 dB, a DC gain of about 72+31=103 dB issufficient. A DC gain lower then this would mean the amplifier needs tobe designed such that the gain with output swing needs to be linear to12-bit.

[0062] Several amplifier architectures can be used to implement thecircuitry of the present invention. Some of these possibilities will nowbe discussed.

[0063] In one embodiment, a single stage amplifier with the compensationcapacitor being the load capacitor is used. This embodiment is notpreferred, however, because the required DC gain of 103 dB is difficultto achieve. Also the unity gain-bandwidth is very high, on the order of1.86 GHz. This leads to some difficult to realize design constraints.

[0064] Another embodiment utilizes a two-stage Miller compensatedamplifier. This option is certainly a lower power solution compared to asingle stage design, but still has some disadvantages. For example, thebandwidth is provided by only one stage. In addition, most of the poweris consumed to get the phase margin. This solution is also lesspreferred since an increase in load capacitance can affect the settlingperformance and it is difficult to handle varying load and gainrequirements.

[0065] The preferred embodiment utilizes a cascaded architecture. Thisarchitecture was found to be most suitable to handle the tightconstraints. The architecture is discussed in detail below and is shownconceptually in FIG. 6. The cascaded amplifier comprises a two stageamplifier including an input stage (pre-amplifier stage) 60 and anoutput stage (main amplifier stage or gain stage) 62. Capacitors 64 and66, typically parasitic capacitances, are illustrated to symbolize theloading at these nodes.

[0066] The characteristics of the individual amplifier stages 60 and 62and the overall amplifier 30 are shown in FIG. 7. To obtain stability,the first non-dominant pole should be at least at 2*fcl (106 MHz in thisexample). The first stage 60 is essentially a pre-amplifier and thesecond stage 62 is the main gain providing amplifier. The pre-amplifierstage 60 is designed such that its dominant pole is at 2*fcl. Thenon-dominant pole of the main amplifier is placed at a much higherfrequency. Since the PGA range is wide, the pre-amplifier gain is variedto ensure stability. Pre-amplifier gain is flat up to 106 Mhz across allgains. The gain at 53 Mhz is the product of the gain provided by eachamp at that frequency. According to specification followed in developingthe preferred embodiment, this gain is required to be 31 dB.

[0067] The complete amplifier is shown in FIGS. 8a-8 c, where FIG. 8ashows the pre-amplifier or input stage 60, FIG. 8b shows the mainamplifier or output stage 62, and FIG. 8c shows the AC coupling betweenthe two stages 60 and 62.

[0068] Referring first to FIG. 8a, the pre-amplifier stage includes anNMOS input 70, 72. The NMOS diode load pre-amplifier architecture 74 ischosen as it satisfies a number of design goals. The stage has highbandwidth (only NMOS in signal path). The stage provides easilycontrollable variable gain for different PGA gain settings to ensurestability of structure. With an NMOS input and NMOS load, the gainremains controlled across process comers. The unity gain bandwidth (UGB)also tracks well. The gain is controlled digitally by bringing in extradiodes as shown in FIG. 8a. The stage also provides high input commonmode range, which can be important since signal common mode varies overa wide range.

[0069] Referring to FIG. 8b, the main amplifier stage 62 provides formost of the amplifier's gain and some bandwidth. In the preferredembodiment, a regulated telescopic amplifier is used as it uses an allN-channel signal path for best speed and gain performance.

[0070] As shown in FIG. 8c, AC coupling is utilized to couple the firststage 60 and the second stage 62. To maximize the output swing, anoptimal input common-mode voltage (VICM2) is utilized for the mainamplifier. Unfortunately, this voltage is not equal to the output commonmode voltage of the previous stage, i.e., the pre-amplifier stage. Tode-couple these, the first stage output is capacitively coupled to themain amplifier stage input.

[0071] Results of a test version of the analog pre-processor of thepreferred embodiment are shown in FIGS. 9 and 10. The PGA gain linearityhas been found to be within +/−0.4 dB, less than the goal of +/−0.5 dB.FIG. 9 shows the measured gain as a function of digital code. Thedeviation of measured PGA gain from ideal gain is shown in FIG. 10.

[0072] While this invention has been described with reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. It is therefore intended that the appended claimsencompass any such modifications or embodiments.

What is claimed is:
 1. A digital imaging device comprising: a lightsensor including an optical input and an analog electrical output; ananalog pre-processor including an analog input and an analog output, theanalog input coupled to the analog electrical output of the imagingdevice, the analog pre-processor including one and only one amplifier;an analog-to-digital converter including an analog input and a digitaloutput, the analog input of the analog-to-digital converter coupled tothe analog output of the analog pre-processor; and a digital processingcircuit including a digital input coupled to the digital output of theanalog-to-digital converter.
 2. The device of claim 1 wherein theimaging device includes a matrix array of optical inputs.
 3. The deviceof claim 1 wherein the imaging device comprises a charge coupled device(CCD).
 4. The device of claim 1 wherein the imaging device comprisesCMOS integrated sensor (CIS).
 5. The device of claim 1 wherein theamplifier comprises a two stage amplifier that includes an input stageand an output stage.
 6. The device of claim 5 wherein the amplifierutilizes AC coupling between the input stage and the output stage. 7.The device of claim 5 wherein the input stage is optimized for largecommon mode variation and the output stage has a dynamic range that isoptimized for large output swing.
 8. The device of claim 1 wherein theamplifier includes a positive input node, a negative input node, apositive output node and a negative output node, the analogpre-processor further comprising: a first variable capacitor coupledbetween the negative input node and the analog electrical output of theimaging device; a second variable capacitor coupled between the positiveinput node and a reference voltage node; a third variable capacitorcoupled between the positive input node and the negative output node; afourth variable capacitor coupled between the negative input node andthe positive output node; a first switch coupled in series with thethird variable capacitor and between the negative input node and thepositive output node; and a second switch coupled in series with thefourth variable capacitor and between the negative input node and thepositive output node.
 9. The device of claim 1 wherein the digitalprocessing circuit comprises a digital signal processor.
 10. The deviceof claim 1 wherein the digital processing circuit comprises anapplication specific integrated circuit (ASIC).
 11. The device of claim1 and further comprising a storage device with an input coupled to anoutput of the digital processing circuit.
 12. The device of claim 1 andfurther comprising a display device with an input coupled to an outputof the digital processing circuit.
 13. An analog circuit comprising: anamplifier including a first input node, a second input node, a firstoutput node and a second output node; a first variable capacitor coupledbetween the first input node and an analog signal node; a secondvariable capacitor coupled between the second input node and a referencevoltage node; a third variable capacitor coupled between the first inputnode and the second output node; a fourth variable capacitor coupledbetween the second input node and the first output node; a first switchcoupled in series with the third variable capacitor and between thefirst input node and the second output node; and a second switch coupledin series with the fourth variable capacitor and between the secondinput node and the first output node.
 14. The circuit of claim 13wherein the amplifier comprises a two stage amplifier including an inputstage and an output stage.
 15. The circuit of claim 14 wherein theamplifier utilizes AC coupling between the input stage and the outputstage.
 16. The circuit of claim 15 wherein the input stage is optimizedfor large common mode variation.
 17. The circuit of claim 15 wherein theoutput stage has a dynamic range that is optimized for large outputswing.
 18. The circuit of claim 13 and further comprising: a thirdswitch coupled between the first input node and a input common node; afourth switch coupled between the second input node and the input commonnode; a fifth switch coupled between the first output node and the inputcommon node; and a sixth switch coupled between the second output nodeand the input common node.
 19. The circuit of claim 18 wherein thethird, fourth, fifth and sixth switches are each responsive to a resetsignal.
 20. The circuit of claim 13 wherein the analog signal nodecomprises a CCD input node.
 21. The circuit of claim 13 wherein each ofthe first, second, third and fourth variable capacitors comprises aplurality of fixed capacitors.
 22. The circuit of claim 13 wherein thefirst input node comprises a positive input node, the second input nodecomprises a negative input node, the first output node comprises apositive output node and the second output node comprises a negativeoutput node.
 23. A signal processing method comprising: receiving ananalog electrical signal; sampling the analog electrical signal at afirst time and at a second time; determining the difference between theanalog electrical signal sampled at the first time and the analogelectrical signal sampled at the second time; amplifying the differencewith a first gain; capacitively providing the amplified difference to asecond amplifier stage; and amplifying the amplified difference with asecond gain to obtain a digitizable analog signal.
 24. The method ofclaim 23 and further comprising: receiving an optical signal; andconverting the optical signal into the analog electrical signal.
 25. Themethod of claim 23 and further comprising digitizing the digitizableanalog signal.
 26. The method of claim 23 wherein the steps ofamplifying the difference and amplifying the amplified difference areperformed by a single amplifier, the single amplifier including a firstamplifier stage with the first gain and the second amplifier stage withthe second gain.